1. Field of the Invention
The present invention relates generally to integrated circuits, and more particularly to methods and apparatuses for improved memory self-timing circuitry.
2. Description of the Related Art
Currently, semiconductor memory cores are laid-out in an array format, such that each individual core cell is coupled to a wordline and a pair of differential bitlines. Access to data stored in a selected core cell generally is provided by associated memory accessing circuitry designed around the memory core. This memory accessing circuitry typically includes addressing circuitry for selecting a core cell, wordline drivers for driving a selected wordline, and sense amplifiers for amplifying the signal read from the selected core cell.
For ease of understanding, FIG. 1 shows a block diagram of a memory bank having a memory core 100 and associated access circuitry. As in conventional memory core designs, a plurality of core cells 102 is arrayed throughout the memory core 100. In this example, a control block circuit 110 is used to control access to selected memory core cells 102 using wordline drivers 106 and sense amplifiers (SA) 104.
As shown in FIG. 1, the control block circuit 110 is configured to produce a signal 116a that triggers a selected wordline driver 106 upon a rising edge of the signal 116a. When the signal 116a experiences a falling edge (ie., at a time determined by a conventional self-timing architecture described below), a signal 116b initiates the sensing of data through the selected sense amplifiers 104. As shown, the wordline drivers 106 are connected to each of the core cells 102 via wordlines, which interconnect each of the core cells 102 in a horizontal direction. In a like manner, the sense amplifiers 104 are connected to each of the core cells 102 in the vertical direction, through the use of differential bitlines.
In a conventional memory block, designers have used a self-timing architecture that enables each memory bank to determine when the sense amplifiers 104 should commence sensing data from the core cells 102 in the memory core 100. Self-timing architectures generally are used to approximate a standard delay time (i.e., generally the worst case timing delay for a given core cell), which will be used when accessing the core cells 102. The self-timing architecture is utilized because the actual delay time of a particular core cell 102 can vary from other core cells in the memory core depending on the location of the particular core cell 102. By way of example, a particular core cell 103 is located at the furthest location from a given wordline driver 106 and a given sense amplifier 104.
Therefore, an RC delay associated with the wordline that couples the wordline driver 106 to the core cell 103, and the RC delay associated with the bitlines that couple a sense amplifier 104 to the core cell 103, will have a combined RC delay that is larger than any other core cell 102 in the memory core 100. For example, the combined RC delay of the wordline and the bitlines that couple to a core cell 101, will be smaller than any other core cell of the memory core 100. Therefore, a self-timing architecture which includes a model wordline driver 106xe2x80x2, core cells 102xe2x80x2, a model core cell 103xe2x80x2, a model wordline 112a, model bitlines 112b, sense amplifier 104xe2x80x2, and a self-timing return path 114 serves to establish the aforementioned standard delay time.
Accordingly, the self-timing architecture is well suited to estimate when enough bitline differential has been achieved (i.e., due to the worst case model core cell 103xe2x80x2) to correctly perform a sense amplification to read the data of a given core cell 102 in the memory core 100. In operation, the control block circuitry initiates the select signal 116a to the model wordline driver 106xe2x80x2 to access the model core cell 103xe2x80x2. When the model core cell 103xe2x80x2 has been accessed, a signal is passed through the model bitlines 112b, through sense amplifier 104xe2x80x2 and along the self-timing return path 114, that communicates to the control block circuit 110. When using a multi-bank memory, the above described self-timing structure is duplicated in each memory bank, as shown in FIG. 2.
FIG. 2 is a diagram showing a prior art multi-bank memory 200. As shown, the prior art multi-bank memory 200 includes a plurality of memory banks B0 to Bn, each in communication with a plurality of global wordlines 208, which are generated by a plurality of global wordline drivers 202. In addition, each memory bank B0-Bn is in communication with a global control block 204, which provides control signals for the global wordline drivers and the global sense amps 206.
As described above, each memory bank B0-Bn includes a memory core 100a-100n having a plurality of core cells, each accessed using the local wordline drivers 106. Further, each memory bank B0-Bn includes a model row having a model wordline driver 106xe2x80x2, core cells 102xe2x80x2, and a model core cell 103xe2x80x2. A model column having a plurality of core cells 102xe2x80x2, model bitlines, and a sense amplifier 104xe2x80x2 is also included in each memory bank B0-Bn. In addition, a self-timing path 114 serves to establish the standard delay time for the local control block 10 of each memory bank.
Unfortunately, as shown if FIG. 2, the prior art self-timing architecture requires a model column of core cells 102xe2x80x2, model bitlines, and a sense amplifier 104xe2x80x2 on each memory bank. As a result, the prior art self-timing architecture requires a large amount of area for the model columns, which increases cost and reduces the area available for functional core cells. Thus, in view of the foregoing, there is a need for a self-timing architecture that requires less area than conventional self-timing architectures in multi-bank memories.
Broadly speaking, the present invention fills these needs by providing a self-timing architecture that utilizes a single global timing column per row of memory banks to provide self-timing synchronization. In one embodiment, a self-timing system for a memory device is disclosed. The self-timing system includes a dummy global wordline signal, which is configured to follow a global timing pulse for a memory device. In addition, a row of at least two non-timing memory banks is included. Each non-timing memory bank includes a model row in electrical communication with the dummy global wordline signal. Each model row is comprised of a plurality of load cells. The self-timing system further includes a timing memory bank having a global timing column. The global timing column is comprised of a plurality of load cells that are coupled via a pair of bitlines. In operation, the global timing column responds to the dummy global wordline signal to provide a self-timing reset signal for the memory device. In this manner, the self-timing reset signal is provided to each active memory bank in the row of memory banks.
In one aspect, the timing memory bank, which includes the global timing column, can be located such that the global timing column responds slower to global wordlines than all other core cells in the row of memory banks. That is, the timing memory bank is located such that the global timing column represents the worst case timing. Generally, the load cells can be core cells, however, in some aspects the load cells can be transistors configured to mimic a load of a core cell. The timing memory bank can include a model row of load cells that are in communication with an active dummy local wordline signal, which is configured to follow the dummy global wordline signal. Further, the model row in each non-timing memory bank can be in communication with a non-active dummy local wordline signal, which is configured to have a low value. To design the self-timing system, a generator can be used.
In a further embodiment, a method is disclosed for self-timing synchronization for a row of memory banks in a memory device. A dummy global wordline signal is provided to at least three memory banks. As above, each memory bank includes a model row in electrical communication with the dummy global wordline signal. Also, each model row is comprised of a plurality of load cells. A self-timing reset signal for the memory device is provided using a single global timing column, which is in electrical communication with the dummy global wordline signal. As above, the global timing column includes a plurality of load cells. In this manner, each active memory bank in the row of memory banks is reset using the self-timing reset signal.
A memory device having a self-timing system for each row of memory banks is disclosed in a further embodiment of the present invention. The memory device includes a plurality of global wordlines drivers, which provide a plurality of global wordline signals to a row of memory banks. Each global wordline signal is configured to follow a global timing signal when the particular global wordline is selected. The memory device further includes a dummy global wordline signal that is configured to follow a global timing pulse. The row of memory banks includes at least two non-timing memory banks, each including a model row in electrical communication with the dummy global wordline signal. As above, each model row is comprised of a plurality of load cells. The row of memory banks further includes a timing memory bank having a global timing column that is comprised of a plurality of load cells coupled via at least one bit line. The global timing column responds to the dummy global wordline signal to provide a self-timing reset signal for the memory device. In this manner, the self-timing reset signal is provided to each active memory bank in the row of memory banks. In one aspect, the timing memory bank is located further from the global wordline drivers than each nontiming memory bank. As above, the memory device can be designed using a generator.
Advantageously, embodiments of the present invention utilize less area than conventional self-timing architectures for providing self-timing. In particular, by using a single global timing column in a row of memory banks, embodiments of the present save area on memory devices. Other aspects and advantages of the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.